The present invention relates generally to memory sense amplifiers, and more specifically to reference level generation with offset compensation for a sense amplifier.
Contemporary memory access circuits rely on differential sense amplifiers to read small signals generated by a selected memory cell from a memory device such as a dynamic random access memory (DRAM) device. These sense amplifiers typically use transistors configured in a cross-coupled fashion to amplify a small voltage differential created by the cell. This cross-coupled configuration of the transistors is used to tolerate global variation in device threshold by relying on device matching of the transistors as opposed to the absolute threshold voltages of the transistors. As semiconductor device technology continues to evolve towards providing smaller device sizes and more devices per integrated circuit (IC) (and thus smaller voltages utilized within the circuits within the IC), there is an increase in local device mismatch caused by random variation, including random dopant fluctuation and line edge roughness. Consequently, the increase in device mismatch requires more of a signal from the memory cell to reliably overcome the device mismatch, resulting in larger and slower memories.